Project 125%
Torture a Bit
Run the double-well simulation at three barrier heights, count how often heat flips the bit, and chart how a taller barrier quiets it. One script and one chart — no report.
Full specification: Torture a Bit →Fall 2026 · Section 001 · Class #4393 · 3 credits
ENGR 255
Physical Foundations of Digital Engineering
This course addresses the basic principles governing the physical realization of computing systems and their relationship to performance, energy, and robustness. It begins with the question of what it physically takes to represent and reliably change a single bit, and builds up through CMOS devices, interconnect, and timing to complete digital systems. The physical limits of CMOS are examined, and analog, quantum, and biological computing are introduced. The treatment is practical and model-driven: students build and validate computational models of the devices and circuits under study rather than working from closed-form derivations alone.
Mon & Wed 6:00 – 7:50 PM
Online — all sessions live on Google Meet
Room of record: Pratt 520
Dial in: +1 631-769-5311 · PIN 233 399 950# · more numbers
Lecture notes
Session Notes
Posted before the session they're used in and kept available all term. Each set is a self-contained page — read it, work the examples, and bring questions.
01
From Physics to Computation
WEEK 1 · S1 · SEP 2 02 Representing a Bit
WEEK 2 · S2 · SEP 9 03 The Physical Cost of Reliability
WEEK 3 · S3–S4 · SEP 14, SEP 16 04 Silicon: The Switchable Material
WEEK 4 · S5–S6 · SEP 21, SEP 23 05 The Transistor: A Barrier with a Knob
WEEK 5 · S7–S8 · SEP 28, SEP 30 06 Switches, Inverters, and Static CMOS Gates
WEEK 6 · S9–S10 · OCT 5, OCT 7 07 Combinational Logic and Physical Composition
WEEK 7 · S11–S12 · OCT 12, OCT 14 08 Every Wire Is a Bucket
WEEK 8 · S13–S14 · OCT 19, OCT 21 09 The Wire Is a Place
WEEK 9 · S15–S16 · OCT 26, OCT 28 10 The Slowest Route Sets the Clock
WEEK 10 · S17–S18 · NOV 2, NOV 4 11 Follow the Money
WEEK 11 · S19–S20 · NOV 9, NOV 11 12 Taller Than the Hum
WEEK 12 · S21–S22 · NOV 16, NOV 18
WEEK 1 · S1 · SEP 2 02 Representing a Bit
WEEK 2 · S2 · SEP 9 03 The Physical Cost of Reliability
WEEK 3 · S3–S4 · SEP 14, SEP 16 04 Silicon: The Switchable Material
WEEK 4 · S5–S6 · SEP 21, SEP 23 05 The Transistor: A Barrier with a Knob
WEEK 5 · S7–S8 · SEP 28, SEP 30 06 Switches, Inverters, and Static CMOS Gates
WEEK 6 · S9–S10 · OCT 5, OCT 7 07 Combinational Logic and Physical Composition
WEEK 7 · S11–S12 · OCT 12, OCT 14 08 Every Wire Is a Bucket
WEEK 8 · S13–S14 · OCT 19, OCT 21 09 The Wire Is a Place
WEEK 9 · S15–S16 · OCT 26, OCT 28 10 The Slowest Route Sets the Clock
WEEK 10 · S17–S18 · NOV 2, NOV 4 11 Follow the Money
WEEK 11 · S19–S20 · NOV 9, NOV 11 12 Taller Than the Hum
WEEK 12 · S21–S22 · NOV 16, NOV 18
Fifteen weeks
Weekly Schedule
The schedule is aligned to the LIU Brooklyn academic calendar; any session affected by a University holiday or closure is adjusted and announced in class and on Brightspace. The current week is highlighted.
| Week | Sessions | Topic | Materials | To do |
|---|---|---|---|---|
| WK 1 | S1 · Sep 2 | Course overview. From physics to computation: the digital abstraction | Notes 01 |
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| WK 2 | S2 · Sep 9 | Representing a bit: distinguishability, state change, and the barrier model◦ Sep 7 — no class (Labor Day) | Notes 02 |
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| WK 3 | S3–S4 · Sep 14, Sep 16 | Energy, entropy, and thermal noise. The physical cost of reliability | Notes 03 |
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| WK 4 | S5–S6 · Sep 21, Sep 23 | Semiconductor physics essentials for the digital engineer | Notes 04 |
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| WK 5 | S7–S8 · Sep 28, Sep 30 | MOSFET device physics: structure, operating regions, and models | Notes 05 |
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| WK 6 | S9–S10 · Oct 5, Oct 7 | Switches as computing devices. CMOS inverter and static logic families | Notes 06 |
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| WK 7 | S11–S12 · Oct 12, Oct 14 | Interconnected switches: combinational logic and physical composition | Notes 07 |
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| WK 8 | S13–S14 · Oct 19, Oct 21 | RC circuit analysis and delay modeling of gates and loads Project 1 due (Oct 19) |
Notes 08 |
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| WK 9 | S15–S16 · Oct 26, Oct 28 | Wires: signal propagation, transmission-line behavior, and communication cost | Notes 09 |
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| WK 10 | S17–S18 · Nov 2, Nov 4 | Performance: critical path, delay budgets, and speed analysis | Notes 10 |
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| WK 11 | S19–S20 · Nov 9, Nov 11 | Energy: dynamic and static power, and the energy-delay trade-off Project 2 due (Nov 9) |
Notes 11 |
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| WK 12 | S21–S22 · Nov 16, Nov 18 | Robustness: noise margins, thermal and coupling noise, and error Project 3 due (Nov 16) |
Notes 12 |
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| WK 13 | S23–S24 · Nov 23, Nov 25 | Sequential logic, clocking, timing closure, and metastability. FSM and Turing models Capstone proposal due |
Notes 13 · soon |
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| WK 14 | S25–S26 · Nov 30, Dec 2 | Memory, input/output, and the physical limits of CMOS. CMOS analog computing | Notes 14 · soon |
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| WK 15 | S27–S28 · Dec 7, Dec 9 | Alternative models: quantum and biological computing. Capstone presentations | Notes 15 · soon |
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| FINALS | Dec 14 – 21 | Final capstone deliverables due. No final examination. | ||
No examinations
Projects & Grading
This course is graded entirely on four hands-on projects — there are no exams. Specifications and rubrics are released at least two weeks before each due date. Every project is submitted as a Git repository plus a written report; late work is reduced by 10% per calendar day.
Project 225%
Race a Bucket Brigade
Race a bare wire against a repeatered one with the provided bucket-brigade script, watch the parabola lose to the straight line, and turn one knob to move the crossover. One chart — no report.
Full specification: Race a Bucket Brigade →Project 325%
Find the Redline
Every chip has a redline — the clock where the slowest route stops keeping up. Find yours with the provided script (Notes 10's 360 ps specimen), then grab the voltage dial and move it. One script and one chart — no report.
Full specification: Find the Redline →Project 425%
Capstone: Beyond CMOS
Select a non-CMOS computing technology — analog, quantum, biological, or another approved alternative — and produce a design study applying speed, energy, and reliability analysis to a specific computational task, with a defensible comparison against a CMOS baseline. Model, technical report, and a live presentation.
Specification released in classGrading rubric — how every project is assessed
Every project is graded on the same four criteria. Each project rubric is released with its specification.
| Criterion | Weight | What is assessed |
|---|---|---|
| Correctness and completeness | 35% | The artifact does what the specification requires, and the required cases are handled. |
| Implementation quality | 20% | Structure, readability, and evidence of testing. Commit history shows sustained individual work. |
| Analysis and written report | 25% | The report explains the design, justifies the decisions, and reports results honestly, including what did not work. |
| Demonstration and defense | 20% | The student can run the artifact live and answer questions about any part of it. |
Grading scale
| Letter | Range % | GPA |
|---|---|---|
| A | 93–100 | 4.00 |
| A- | 90–92 | 3.67 |
| B+ | 87–89 | 3.33 |
| B | 83–86 | 3.00 |
| B- | 80–82 | 2.67 |
| C+ | 77–79 | 2.33 |
| C | 73–76 | 2.00 |
| C- | 68–72 | 1.67 |
| D | 60–67 | 1.00 |
| F | < 60 | 0.00 |
Expected time commitment (160 h total)
| Synchronous class sessions | 51 h |
| Review of posted notes | 30 h |
| Project 1 — Torture a Bit | 17 h |
| Project 2 — Race a Bucket Brigade | 20 h |
| Project 3 — Find the Redline | 20 h |
| Project 4 — Capstone and presentation | 22 h |
| Total | 160 h |
The fine print
Course Info & Policies
Prerequisites
College-level physics and mathematics through calculus, and programming proficiency in a language of your choice, or permission of the instructor.
Software & tools — all free
- Python 3.11 or later with NumPy, SciPy, and Matplotlib (for modeling and analysis)
- ngspice or LTspice (circuit simulation)
- Logisim Evolution (logic-level design and exploration)
- Git and a personal GitHub account
- Google Meet, for all synchronous class sessions
What you'll be able to do
- Perform speed and energy analysis of devices and circuits used as digital logic elements.
- Derive the computational power of both finite (FSM) and infinite (Turing) models of computation.
- Derive and compute noise limits (thermal, coupling, and other) in digital devices and interconnect.
- Apply speed, energy, and reliability properties of CMOS to the design of simple CMOS digital circuits.
- Apply speed, energy, and reliability properties to the design of at least one non-CMOS technology.
- Communicate a physical-design analysis in written form and in a technical presentation.
Live sessions & attendance
All class sessions are held live on Google Meet at the scheduled times. Students are expected to attend, to have their development environment running, and to be able to share their screen when demonstrating work. Every student presents current work and takes part in critique at each meeting.
Communication
Modes of communication are Brightspace (lms.liu.edu) and email; expect a reply within 24 hours. Virtual office hours are held by appointment — email the instructor to schedule.
Materials & this site
All course notes, examples, and project specifications are distributed through the course repository and this site. Students are responsible for reviewing the current version before each session.
Submission & late work
Every project is submitted through Brightspace as a link to the student's Git repository, together with the written report. Commit history is part of the evidence of individual work. Late work is reduced by 10% per calendar day. Extensions are granted only for a documented medical or family emergency, requested before the deadline by email.
Individual work & AI use
Projects are individual work unless a specification explicitly designates a team deliverable. Discussing approaches is fine, but submitted code, models, and writing must be your own. Generative AI tools may be used as a learning aid and are treated like any other reference: any AI-assisted portion of a submission must be disclosed in the project report, and you must be able to explain and defend every line of what you submit.
Recording
Recording of class sessions by students is not permitted without the instructor's prior written consent.
Accommodations
Students with a documented disability/impairment who require reasonable accommodations should provide an Accommodation Letter from Student Support Services (Sloan Building, 1st Floor · 718-488-1044 · studentsupportservices@brooklyn.liu.edu · Mon–Fri 9am–5pm).
Technical issues
For issues with Brightspace, LIU email, Google Meet, or campus network access, contact IT: It@liu.edu · 718-488-3300 (Mon–Fri 9am–5pm).