This course addresses the basic principles governing the physical realization of computing systems and their relationship to performance, energy, and robustness. It begins with the question of what it physically takes to represent and reliably change a single bit, and builds up through CMOS devices, interconnect, and timing to complete digital systems. The physical limits of CMOS are examined, and analog, quantum, and biological computing are introduced. The treatment is practical and model-driven: students build and validate computational models of the devices and circuits under study rather than working from closed-form derivations alone.
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Posted before the session they're used in and kept available all term. Each set is a self-contained page — read it, work the examples, and bring questions.
The schedule is aligned to the LIU Brooklyn academic calendar; any session affected by a University holiday or closure is adjusted and announced in class and on Brightspace. The current week is highlighted.
| Week | Sessions | Topic | Materials | To do |
|---|---|---|---|---|
| WK 1 | S1 · Sep 2 | Course overview. From physics to computation: the digital abstraction | Notes 01 |
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| WK 2 | S2 · Sep 9 | Representing a bit: distinguishability, state change, and the barrier model◦ Sep 7 — no class (Labor Day) | Notes 02 |
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| WK 3 | S3–S4 · Sep 14, Sep 16 | Energy, entropy, and thermal noise. The physical cost of reliability | Notes 03 |
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| WK 4 | S5–S6 · Sep 21, Sep 23 | Semiconductor physics essentials for the digital engineer | Notes 04 · soon |
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| WK 5 | S7–S8 · Sep 28, Sep 30 | MOSFET device physics: structure, operating regions, and models Project 1 due |
Notes 05 · soon |
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| WK 6 | S9–S10 · Oct 5, Oct 7 | Switches as computing devices. CMOS inverter and static logic families | Notes 06 · soon |
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| WK 7 | S11–S12 · Oct 12, Oct 14 | Interconnected switches: combinational logic and physical composition | Notes 07 · soon |
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| WK 8 | S13–S14 · Oct 19, Oct 21 | RC circuit analysis and delay modeling of gates and loads Project 2 due |
Notes 08 · soon |
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| WK 9 | S15–S16 · Oct 26, Oct 28 | Wires: signal propagation, transmission-line behavior, and communication cost | Notes 09 · soon |
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| WK 10 | S17–S18 · Nov 2, Nov 4 | Performance: critical path, delay budgets, and speed analysis | Notes 10 · soon |
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| WK 11 | S19–S20 · Nov 9, Nov 11 | Energy: dynamic and static power, and the energy-delay trade-off | Notes 11 · soon |
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| WK 12 | S21–S22 · Nov 16, Nov 18 | Robustness: noise margins, thermal and coupling noise, and error Project 3 due |
Notes 12 · soon |
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| WK 13 | S23–S24 · Nov 23, Nov 25 | Sequential logic, clocking, timing closure, and metastability. FSM and Turing models Capstone proposal due |
Notes 13 · soon |
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| WK 14 | S25–S26 · Nov 30, Dec 2 | Memory, input/output, and the physical limits of CMOS. CMOS analog computing | Notes 14 · soon |
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| WK 15 | S27–S28 · Dec 7, Dec 9 | Alternative models: quantum and biological computing. Capstone presentations | Notes 15 · soon |
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| FINALS | Dec 14 – 21 | Final capstone deliverables due. No final examination. | ||
This course is graded entirely on four hands-on projects — there are no exams. Specifications and rubrics are released at least two weeks before each due date. Every project is submitted as a Git repository plus a written report; late work is reduced by 10% per calendar day.
Build a computational model of a bit held by an energy barrier, and determine the minimum barrier height and switching energy required for a specified error rate at a specified temperature. The written component relates the model to thermal noise limits and to the observed behavior of real devices.
Design a small CMOS logic block, simulate it, and characterize its propagation delay, dynamic and static power, and noise margins across a range of supply voltages and loads. Deliverables include the simulation files and an energy-delay trade-off analysis.
Model the RC behavior of the interconnect in a small datapath, determine the maximum clock frequency the physical layer permits, and analyze coupling noise between adjacent lines. The written component identifies which physical effect binds the design and why.
Select a non-CMOS computing technology — analog, quantum, biological, or another approved alternative — and produce a design study applying speed, energy, and reliability analysis to a specific computational task, with a defensible comparison against a CMOS baseline. Model, technical report, and a live presentation.
Every project is graded on the same four criteria. Each project rubric is released with its specification.
| Criterion | Weight | What is assessed |
|---|---|---|
| Correctness and completeness | 35% | The artifact does what the specification requires, and the required cases are handled. |
| Implementation quality | 20% | Structure, readability, and evidence of testing. Commit history shows sustained individual work. |
| Analysis and written report | 25% | The report explains the design, justifies the decisions, and reports results honestly, including what did not work. |
| Demonstration and defense | 20% | The student can run the artifact live and answer questions about any part of it. |
| Letter | Range % | GPA |
|---|---|---|
| A | 93–100 | 4.00 |
| A- | 90–92 | 3.67 |
| B+ | 87–89 | 3.33 |
| B | 83–86 | 3.00 |
| B- | 80–82 | 2.67 |
| C+ | 77–79 | 2.33 |
| C | 73–76 | 2.00 |
| C- | 68–72 | 1.67 |
| D | 60–67 | 1.00 |
| F | < 60 | 0.00 |
| Synchronous class sessions | 51 h |
| Review of posted notes | 30 h |
| Project 1 — Bit Representation and Noise | 17 h |
| Project 2 — CMOS Logic: Speed and Energy | 20 h |
| Project 3 — Interconnect and Timing | 20 h |
| Project 4 — Capstone and presentation | 22 h |
| Total | 160 h |
College-level physics and mathematics through calculus, and programming proficiency in a language of your choice, or permission of the instructor.
All class sessions are held live on Google Meet at the scheduled times. Students are expected to attend, to have their development environment running, and to be able to share their screen when demonstrating work. Every student presents current work and takes part in critique at each meeting.
Modes of communication are Brightspace (lms.liu.edu) and email; expect a reply within 24 hours. Virtual office hours are held by appointment — email the instructor to schedule.
All course notes, examples, and project specifications are distributed through the course repository and this site. Students are responsible for reviewing the current version before each session.
Every project is submitted through Brightspace as a link to the student's Git repository, together with the written report. Commit history is part of the evidence of individual work. Late work is reduced by 10% per calendar day. Extensions are granted only for a documented medical or family emergency, requested before the deadline by email.
Projects are individual work unless a specification explicitly designates a team deliverable. Discussing approaches is fine, but submitted code, models, and writing must be your own. Generative AI tools may be used as a learning aid and are treated like any other reference: any AI-assisted portion of a submission must be disclosed in the project report, and you must be able to explain and defend every line of what you submit.
Recording of class sessions by students is not permitted without the instructor's prior written consent.
Students with a documented disability/impairment who require reasonable accommodations should provide an Accommodation Letter from Student Support Services (Sloan Building, 1st Floor · 718-488-1044 · studentsupportservices@brooklyn.liu.edu · Mon–Fri 9am–5pm).
For issues with Brightspace, LIU email, Google Meet, or campus network access, contact IT: It@liu.edu · 718-488-3300 (Mon–Fri 9am–5pm).