Every Wire Is a Bucket

1The lie we've been telling

For two weeks we have spoken as if gates answer instantly: flip the input, and the output is simply there, the way a redstone lamp seems to light the moment you throw the lever. Notes 06 even confessed in a footnote that this was a loan — "torch ticks are like gate delay; that is week 8" — and Notes 07 ended with a garden hose filling buckets and a promise of real numbers. This is week 8. Time to pay up.

The truth: no output changes instantly, because changing an output means moving charge, and charge moves through things that resist it. Look at any wire between two gates — say, an inverter's output running to a NAND's input — and ask what is physically there. The wire itself is a strip of metal that can hold charge. The NAND input it lands on is the gate plate of a transistor: Notes 05 told you the plate and the channel are two sides of a capacitor. So the whole node — wire plus every input hanging on it — is one bucket for charge. Small, but real: a single gate input holds about 10 fF worth.

Now ask what fills it. When the driving gate decides "make a 1", its pull-up network connects the bucket to the supply — through transistors that are switched on. And a switched-on transistor is not a perfect wire; Model 1 from Notes 05 gave it a price tag, the on-resistance R_on, a few thousand ohms. In the water version that we will use all week: the supply is a tank that never runs dry, the on-transistor is a tap of a definite size, and the output node is the bucket under it.

Put the two together and you have the entire origin of digital delay, with nothing left over: filling a bucket through a tap takes time. Not because electrons are slow, and not because the logic is thinking — because a finite flow needs a finite time to deliver a finite amount of charge. Every nanosecond your processor spends computing is, at the bottom, buckets filling and draining. This week we learn to read the fill, price it, and add it up along a chain of gates.

2The bucket and the tap

Open a tap over an empty bucket and watch honestly. At first the water pours in fast. As the bucket fills, the filling slows — and near the top it crawls. (For the real reason in the electrical version: the push that drives charge through the tap is the voltage difference between supply and bucket, and as the bucket's voltage rises toward the supply's, that difference — the pressure — shrinks. Less push, less flow.) So the fill is a fade-in, not a snap, exactly as Notes 05's worked example warned: fast start, long soft landing, and "exactly full" never quite arrives.

You do not need to derive that curve, and in this course we never will. You need to read it, and it has exactly two landmarks worth memorizing. First: after a time equal to R times C, the bucket is about 63% full. The 63 is not magic — it is simply where this particular curve lands after one unit — and the honest way to hold it is: every R×C of time, the fill closes about two-thirds of whatever gap remains. Second: after about 2 to 3 R×C, the gap left is a few percent, and no gate downstream can tell the difference. Practically full.

Why is R×C a time at all? Feel it with the picture: a bigger bucket (more C) holds more water, so it fills slower. A smaller tap (more R) passes less flow, so it fills slower. Multiply the two and the units conspire — ohms times farads literally comes out in seconds. That gives the one formula the whole week runs on:

That unit shortcut is a gift. Chip resistances come in kilohms and chip capacitances in femtofarads, and a kilohm times a femtofarad is exactly a picosecond — multiply the two everyday numbers and you are already in the right unit. Notes 05's worked example did precisely this, two weeks early: 5 kΩ times 10 fF is 50 ps, with "the job is essentially done after about three of those" as the seasoning. That multiplication, promised then, is now officially your ruler. Everything else in these notes is using it in richer and richer situations.

Two things to try. Double R with everything else fixed, then undo it and double C instead: the ruler reading doubles identically both times — the curve cannot tell a narrow tap from a big bucket, which is why one multiplication covers both. Then park time at 1.0 R×C and watch where 63% sits relative to the shaded band: comfortably past the decision zone. The flip has already "happened" for the next gate well before the bucket tops off.

One subtlety the bench shades in for you: the next gate does not wait for a full bucket. Notes 06's cliff curve means an input is read as a solid 1 once it climbs past the top of the forbidden zone, somewhere a little above half way up. That happens early in the fill — before one R×C is out. So "delay ≈ R×C" is not just convenient; it is roughly when the downstream gate actually changes its mind. The remaining 37% of the fill is the signal finishing its climb to a restored, full-margin 1 — which Notes 01 told you is never optional.

For your toolchain, in four lines

You never need the curve's formula in this course, but your simulator uses it under the hood, and drawing it yourself once is worth doing. The exp below is the curve's official name; reading the picture is still the skill.

import numpy as np, matplotlib.pyplot as plt
R, C = 5e3, 10e-15                      # 5 kOhm, 10 fF -> R*C = 50 ps
t = np.linspace(0, 5*R*C, 200)
plt.plot(t/1e-12, 1 - np.exp(-t/(R*C)))  # the one honest curve
plt.axvline(R*C/1e-12, ls='--'); plt.xlabel('time (ps)'); plt.show()

Compare the plot with ngspice's transient analysis of the same R and C — they should sit on top of each other. If they don't, one of your units is lying.

3Two taps, one bucket: the inverter, re-seen

Now re-draw Notes 06's inverter in this week's language. The pull-up network is a tap from the tank: when it switches on, it fills the output bucket toward 1. The pull-down network is a tap to the drain: when it switches on, it empties the bucket toward 0. The seesaw rule — exactly one network on at a time — now reads: one tap open, one tap shut, always. And draining obeys the very same curve as filling, run downhill: fast at first, slower as the bucket nears empty, 63% of the way out after one R×C.

Two consequences fall straight out of the picture. First, rising and falling need not take the same time, because the two taps need not be the same size. Notes 07 told you PMOS is the weaker switch — about half the flow for the same width — so unless the designer widens the pull-up, the 0→1 fill runs through a narrower tap than the 1→0 drain, and the rising edge is the slow one. "The gate's delay" is really two numbers, and a datasheet — or your Project 2 simulation — reports both.

Second, and this is the sentence that makes whole chips analyzable: the bucket a gate must fill is mostly the next gate's input. Stand an inverter in front of an inverter. The first one's output wire runs to the second one's gate plates — and those plates, plus the wire, are the bucket. A gate's speed is not its own private property; it depends on what you hang on its output. Same gate, bigger audience, slower flip. Which brings us directly to the next section.

4One tap, many buckets: fan-out

Notes 07 gave "how many inputs one output drives" its name: fan-out. Here is its price. Wire one gate's output to four gate inputs and all four input buckets sit on the same node, joined by metal into one big shared bucket — four times the capacitance, give or take the wire. The tap did not change. So the ruler says it plainly: four buckets through one tap is about four times the delay. Fan-out is not a little tax; it multiplies.

The honest fix, in one paragraph. When one small gate must drive a crowd, you insert a buffer — Notes 07 §8's "bigger inverter", which in this week's language is simply a bigger tap. The small gate now fills only the buffer's single input bucket, and the buffer, with wide transistors and a low R_on, fills the crowd fast. But read the trade in the same picture: a bigger tap is built from wider plates, so its own input bucket is bigger too — you bought drive strength and paid in load on the gate before. That is why Notes 07's toy model had a sweet spot rather than "bigger is always better", and why its rule of thumb — each stage driving about four copies of itself, the famous FO4 — keeps showing up. FO4 is exactly this arithmetic settling where it likes to sit. The full chain-of-buffers story is week 10's; the trade itself you now own.

5Wires are buckets too

Everything so far counted gate inputs and waved at "plus the wire". For short hops between neighboring gates that wave is honest: a few microns of metal adds a couple of femtofarads — a splash, next to a 10 fF input bucket. But metal holds charge along its whole length, so the longer the wire, the bigger the bucket, with no limit and no mercy. A millimeter of ordinary on-chip wire is roughly 200 fF — one wire wearing the capacitance of twenty gate inputs — and a wire that crosses the whole chip is not a bucket at all. It is a bathtub.

And the bathtub hides a second insult we will only name today: a long thin strip of metal does not just hold charge, it also resists along its length — the wire is part tap as well as part bucket, and both parts grow as the wire gets longer. Where that leads (the delay of a bare wire growing with the square of its length, and what repeaters, fat metal, and honest engineering do about it) is precisely next week's subject. For these notes, carry one rule: short wires are a rounding error; long wires are a load; next week, wires get the whole stage to themselves.

6The slowest path sets the speed

One stage's delay is R×C. A real circuit is stages in a row — and along a chain, delays add. Why simple addition is honest: a gate cannot begin to flip until its own input bucket has filled past the decision zone, so stage two's fill only starts once stage one's is (effectively) delivered. First bucket, then the next, then the next — like Notes 06's torch chains, one tick per torch, except now you know what a tick is made of.

Now look at a circuit with more than one route through it. Different input-to-output paths pass through different gates and different buckets, so they take different times — and the circuit is not done until the laziest one arrives. The slowest route has a name every chip designer says daily: the critical path. "How fast is this circuit?" means exactly "how long is its longest chain of buckets?" — nothing more. A clock, when we finally install one in week 13, must tick no faster than the critical path can finish; and week 10 turns today's one idea into a full trade — delay budgets, and how designers buy back picoseconds. Today, just learn to find the path.

Each gate is a 5 kΩ tap; each label under a wire is that node's bucket. The timeline at the bottom stacks the critical path's stage delays end to end — addition, drawn. Flip the fan-out switch and watch one wire's extra buckets slow the whole circuit: nothing about G2 or G3 changed, yet the finish line moved. That lone observation is most of what a timing engineer does for a living.

7Numbers on a chain

Time to do the whole week in one calculation, house style: nothing but the ruler, applied twice and added.

A closing honesty note, so the simplicity doesn't curdle into false confidence. Real timing tools dress this skeleton in refinements — the tap's R isn't perfectly constant mid-flip, a "done" threshold gets chosen and the 3× seasoning applied, rising and falling get separate books (§3). None of the refinements change the skeleton: resistance times capacitance, added along the slowest path. When a timing report lands on your desk someday, you will already know what every number in it is made of.

→Work before Session 15

Session 15 is Monday, October 26, and the whole session belongs to wires — §5's bathtub, opened up. Before then:

• Review these notes. The memory test: draw the tap, the bucket, and the curve from scratch; mark 63% at one R×C and "call it done" at three; then say out loud why four buckets on one tap means four times the delay.
• Ten minutes per bench. On Bench 2.1, confirm that doubling R and doubling C move the ruler by exactly the same amount, and find how far into the fill the next gate stops reading 0. On Bench 6.1, name the critical path before clicking anything, then flip the fan-out switch and explain where the extra 150 ps physically went.
• Re-run Notes 05's §5 worked example from memory — 5 kΩ, 10 fF — and check you land on 50 ps without looking. That reflex is the week.

→Exercises

Not graded, as always. The tap and the bucket answer all three. Bring your answers, or your stuck points, to Session 15.

1. The fade-in. In your own words: why does the bucket fill fast at first and slower near the top — what is physically shrinking? Then the design question: given that "exactly full" never arrives, why is a digital system allowed not to care? (Notes 06's cliff and Notes 01's forbidden zone are the vocabulary.)
2. The slow stack. Notes 07 said a NAND3's pull-down is three switches in series, and warned that long stacks are slow. Make that warning quantitative in tap language: what do three taps in a row do to the effective R of the path, and therefore to the stage's R×C? Why does widening those transistors help, and what does widening cost the gate that drives them?
3. The lopsided gate. A gate's pull-up tap passes half the flow of its pull-down tap (Notes 07 told you why). Which edge is slower at its output, rising or falling, and roughly by what factor? If a chain alternates inverting gates, why might the chain's delay care about both numbers no matter which data pattern you send?

§Symbols and constants