From Physics to Computation

1How this course runs

ENGR 255 is a three-credit course with a two-hour laboratory folded into it, and it is delivered entirely online in two live 110-minute sessions each week. The lab is not a separate afternoon in a building somewhere; it happens inside our meetings. You will be asked to share your screen, run something, and defend it. That is the shape of every session after this one.

The section is small by design — a handful of students — so it is run as a tutorial rather than a lecture course. Expect to be talking, not listening, for a good part of each meeting. Bring current work to every session, even work that does not run yet. A model that fails in an interesting way is a better use of ninety minutes than a model you finished quietly on Sunday.

There is no textbook and there are no exams

Every note set, worked example, and project specification is written for this course and posted to the course repository before the session that uses it. Supplementary readings are linked week by week, all freely available, none required. Your grade comes entirely from four projects at 25% each:

Each project is a build plus a written analysis, submitted as a link to your Git repository together with the report. Commit history is part of the evidence of individual work, so commit as you go rather than in one heroic push the night before. Specifications and rubrics are released at least two weeks before each due date. Late work loses 10% per calendar day; extensions exist for documented emergencies and must be requested before the deadline, not after.

Generative AI is treated like any other reference. Use it, disclose the AI-assisted portion in your report, and be able to explain and defend every line you submit. The failure mode that gets a project rejected is not "you used a tool" — it is "you cannot explain what you handed in."

The treatment is model-driven

We are not going to derive our way through this material with closed-form expressions on a page. Almost every question worth asking about a real device — how fast is this gate, how much energy does that transition cost, how much noise can this wire tolerate — is answered in practice by building a model, running it, and checking it against measured behavior. So each unit pairs the physics with something you compute: a barrier model in Python, a circuit in ngspice, a logic block in Logisim, a delay budget in a spreadsheet you wrote yourself.

Closed-form results still matter, but mostly as sanity checks. When your simulation says a gate switches in 300 picoseconds and a two-line hand estimate says 12, one of them is wrong and you need both to notice.

2Computation is physical

Here is the claim that organizes the whole course, and it is worth stating flatly before we soften it with detail: computation is a physical process, and every constraint on computing is ultimately a physical constraint. There is no such thing as an abstract bit sitting in an abstract register. Somewhere in the machine, a bit is a quantity of charge on a capacitance, or a magnetic domain orientation, or the phase of a superconducting loop, or a molecule in one of two configurations. To store it, you have to hold matter in a state. To change it, you have to move energy. To read it, you have to distinguish that state from its alternative in the presence of thermal agitation that never turns off.

That framing sounds philosophical for about thirty seconds, until you notice that it predicts things. It predicts that there is a minimum energy to erase a bit, and there is. It predicts that making a device smaller makes it faster and cheaper per operation but also less able to hold its state against thermal noise, and it does. It predicts that a processor's clock frequency is limited not by how clever the logic design is but by how long it takes a voltage to propagate down a piece of metal, and it is. Every headline constraint in modern computing — the end of frequency scaling, the power wall, why memory is slower than logic, why quantum computers need dilution refrigerators — falls out of physics that we will work through this term.

The engineer's version of the claim is more useful than the philosopher's. It is this: the properties you care about in a computing system — how fast it is, how much energy it burns, and how often it is wrong — are set at the physical layer, and they trade against each other. You do not get to optimize all three. Most of what we call design at this level is choosing where in that three-way trade you want to sit, and knowing what the physics will and will not let you buy.

Why a digital engineer should care

You could write correct Verilog for years without knowing any of this. Plenty of people do. The reason to know it is that the digital abstraction — the clean world of 0s and 1s, of gates with delays given in a table, of wires that carry a value from A to B instantly and perfectly — is a contract that hardware works very hard to honor, and every hard problem in modern digital design is a place where the contract is straining. Timing closure is the abstraction straining. Signal integrity is the abstraction straining. Power delivery, metastability, soft errors, process variation, thermal throttling: all of these are the physical layer refusing to stay invisible.

So the course is not "physics for its own sake." It is the answer to the question why does the abstraction cost what it costs, which is exactly the question you need to answer when the abstraction stops holding.

3Levels of abstraction, and where physics enters

Computing systems are built as a stack of abstractions, each one hiding the mess of the layer below it behind a simpler interface. This is the only reason a person can write a web application without knowing what a MOSFET is. The stack looks roughly like this, and it is worth being precise about which layers this course lives in.

The four shaded layers are this course. We start at L1 and build upward; by week 13 we reach the bottom edge of what your architecture courses assume.

Abstraction is not free, and it is not a lie either. A good abstraction is a compressed, mostly-true description of the layer below, with a stated domain of validity. "A NAND gate produces the complement of the AND of its inputs" is true — provided the inputs are held long enough, are within the valid input ranges, the supply is within tolerance, the temperature is in range, and you wait for the propagation delay before you look. Strip those provisos away and the statement becomes false in ways that produce chips that fail one time in ten thousand, which is the worst way for a chip to fail.

Everything in this course is, in a sense, the fine print of the digital abstraction. So let us go read the fine print.

4The digital abstraction

Nature does not hand us 0s and 1s. It hands us voltages, and voltage is a continuous quantity: a node in a circuit can sit at 0.7314 V as easily as at 0.7315 V. The digital abstraction is the decision to throw away almost all of that information and keep only one bit of it — is this node high or low? — and then to build machinery that makes the discarded information genuinely not matter.

The mechanism is a set of four voltage thresholds, agreed on in advance by every gate in the system. Two of them constrain what a gate is allowed to produce, and two constrain what it must be able to accept:

• V_OL — the highest voltage a gate may output when it means 0.
• V_OH — the lowest voltage a gate may output when it means 1.
• V_IL — the highest voltage a gate must still interpret as 0.
• V_IH — the lowest voltage a gate must still interpret as 1.

Together these are called the static discipline: a rule that says if you feed me inputs that are unambiguously valid, I promise to produce an output that is unambiguously valid, and I promise it will be even cleaner than what you gave me. Everything between V_IL and V_IH is the forbidden zone — not forbidden in the sense that a voltage cannot physically be there, but in the sense that no gate promises anything about what it will do with a value in that band. Signals are allowed to pass through it in transit. They are not allowed to stop there.

The slack in the contract is what makes the whole scheme work. Define:

These are the noise margins: how much a valid 0 can be pushed upward, or a valid 1 pulled downward, by anything at all — coupling from a neighboring wire, supply droop, ground bounce, thermal noise, a stray cosmic ray — before the receiving gate can no longer be relied on. A noise margin is a bank account of tolerance, and every physical effect in weeks 9 through 12 is a withdrawal from it.

Notice the asymmetry built into the definition. The output specification is tighter than the input specification: a gate must produce something above V_OH but only has to accept something above V_IH, and V_OH > V_IH. That gap is deliberate. It means each gate hands the next one a signal with margin to spare, which is what makes long chains of logic possible at all — the subject of the next section.

Try dropping V_DD to 0.6 V with the thresholds held at the same fractions. The margins shrink in absolute volts while the noise sources that attack them mostly do not. This is the whole story of low-voltage design, and we return to it in week 11.

The voltage transfer characteristic

Where do the four thresholds come from? Not from a standards committee — from the device physics. Measure a real inverter by sweeping its input from 0 to V_DD and recording the output, and you get its voltage transfer characteristic (VTC): a curve that starts high, falls steeply through a transition region, and ends low. The thresholds V_IL and V_IH are conventionally defined as the two points where the slope of that curve equals −1.

That definition is not arbitrary. Slope is gain. Where |dV_out/dV_in| < 1, a perturbation on the input comes out smaller than it went in — the gate attenuates noise. Where the magnitude of the slope exceeds 1, the gate amplifies it. The unity-gain points are exactly the boundary between the region where the device cleans up its input and the region where it makes things worse, so they are the natural edges of the valid input ranges. A device with a gain that never exceeds 1 anywhere — a resistor divider, say — cannot serve as a logic gate at all, no matter how you label its terminals.

This is the first of five things a physical device needs in order to be usable as a computing element. We will develop all five properly in week 6, but they are worth naming now, because they are the criteria you will apply to your capstone technology in December:

1. Nonlinearity with gain > 1 somewhere in the transfer characteristic, so that small deviations are squeezed out rather than accumulated.
2. Isolation between input and output — what happens downstream must not reach back and change the upstream value.
3. Signal restoration — the output must be a cleaner representation than the input, not merely a copy.
4. Composability — the output of one device must be a legal input to the next, in useful numbers (fan-out), with no per-stage retuning.
5. A gain mechanism with an external energy source — restoration adds energy to the signal, and that energy has to come from somewhere, which in CMOS is the power supply.

Hold on to number 5. It is the hinge between the logical story and the energy story: the price of a clean signal is a power supply. Every joule your processor consumes is, at bottom, the cost of continuously repairing information that thermal physics is continuously degrading.

5Restoration, and why discrete beats continuous

Suppose we tried to compute with continuous values instead — represent a number as a voltage directly, and build circuits that add and multiply those voltages. Analog computers of exactly this kind were built, and for some problems they were excellent. The reason they lost is not that they were slow or hard to program, though they were both. It is that errors in a continuous representation accumulate, and errors in a discrete representation do not.

Consider a chain of N stages, each of which perturbs the value it passes on by some small amount ε — from component tolerance, thermal noise, temperature drift, whatever. In the analog chain, the perturbations add. Random errors accumulate as roughly √N · ε and systematic ones as N · ε; either way the signal is worse at the end than at the start, and there is no operation you can perform in the middle that fixes it, because the circuit has no way of knowing which part of the value it is holding is signal and which part is error.

In the digital chain, every stage performs a decision: is this above the threshold or below it? Having decided, it regenerates a full-swing output. The error does not merely fail to accumulate — it is erased, at every stage, forever, so long as it stayed smaller than the noise margin. That is the entire trick. Digital systems are not error-free; they are systems in which errors below a threshold cost exactly nothing and errors above it cost everything.

Both chains carry the same logical 1 through the same noise. The analog trace wanders; the digital trace is pulled back to the rail at every stage — until one perturbation exceeds the margin, at which point the bit is wrong and stays wrong, cleanly and permanently. Digital failure is not graceful, and that is by design.

Two consequences follow from this that are worth stating explicitly, because they shape everything after week 6.

First, restoration is not free. Pulling a degraded signal back to the rail means driving charge onto a capacitance from the supply, and we will price that transaction in week 3, when the energy story gets numbers. A long logic chain does not just take time; it burns energy proportional to how many times you insisted on cleaning the signal up.

Second, the noise margin is the design parameter that everything else negotiates against. Want more speed? Lower the threshold voltages so devices switch sooner — and give up margin. Want less energy? Lower the supply — and give up margin. Want smaller devices? Smaller capacitances hold less charge per bit — and give up margin. There is no move in this design space that does not touch it.

6Speed, energy, robustness: the three currencies

Three quantities organize everything this course does: how fast a system computes, how much energy it spends doing so, and how often it is wrong. Sections 4 and 5 have already shown them tugging at one another — a noise margin is robustness bought with voltage swing, and restoration is robustness bought with energy from the supply. That tension is not a quirk of CMOS; it is the shape of the whole subject, and it is worth previewing the trade space now, before we have the physics to price any of it precisely.

Read the table as a map rather than a set of rules. The point is that there is no free direction. When someone claims a new device technology is a hundred times better, the first question is always better at which of the three, and what did it give back on the other two? A memristive cell with wonderful energy per write and a ten-year retention problem is not better than CMOS; it is differently placed in the same trade space. Learning to make that comparison rigorously, on a specific computational task rather than in the abstract, is the whole content of Project 4.

Weeks 2 and 3 exist to turn the middle of that table from adjectives into numbers: week 2 builds the model of what it takes to hold a bit at all, and week 3 attaches an energy and an error rate to it. From then on, every unit of the course adds a priced row to this map.

A related habit worth building now: always attach a unit and an operating point to a claim. "Fast" is not a specification; "230 ps propagation delay at 0.9 V, 25 °C, fan-out of 4" is. Every number in your project reports should carry the conditions under which it was obtained, and every simulation you run should record them. Half the errors I see in this course come from comparing two numbers taken at different operating points.

7A digital information processing system

Step back up to the system view and ask what a computing machine actually has to do. Every digital information processing system, from a thermostat to a datacenter, performs four functions, and each one maps to a distinct physical problem that occupies a distinct part of this course.

Communication deserves a preview, because students routinely underestimate it. A signal in an on-chip wire propagates through silicon dioxide with a relative permittivity near 3.9, giving a velocity of roughly c/√3.9 ≈ 1.5 × 10⁸ m/s — about 15 cm per nanosecond. At a 3 GHz clock, that is 5 cm of travel per cycle, and that is the optimistic case where the wire behaves as a transmission line. Most on-chip wires do not; they behave as distributed RC networks, where delay grows with the square of length rather than linearly, and a 1 mm wire can cost more delay than the gate driving it.

The consequence is one of the most important structural facts about modern computers: moving a bit costs more than computing with it. On a current process, a floating-point operation costs on the order of a few picojoules, while fetching its operands from off-chip memory costs hundreds. Locality is not a software nicety; it is a physical-layer constraint that has propagated all the way up the stack to shape cache hierarchies, GPU memory models, and the design of every machine-learning accelerator on the market. We derive the numbers behind it in weeks 8 and 9, and Project 3 makes you find them yourself for a small datapath.

8Where the abstraction leaks — a map of the term

The digital abstraction is a contract, and the rest of this course is a tour of the places the contract strains. Here is the term, framed that way.

One honest caveat about the last two weeks. Alternative computing models attract a great deal of loose talk, and part of what you should get out of this course is the ability to tell a real claim from a press release. The test is always the same three currencies applied to a specific task: what does this technology do faster, at what energy per operation, at what error rate, compared against a CMOS implementation of the same task built with the same effort? Technologies that win somewhere real — and several do — survive that question. Most of the excitement does not.

9Work before Session 2

Session 2 is Wednesday, September 9 — note that there is no class Monday, September 7, for Labor Day. Everything below should be done before we meet, and the first three should be finished tonight during the setup block.

• Install Python 3.11 or later with NumPy, SciPy, and Matplotlib. Verify with a script that imports all three and prints their versions.
• Install ngspice (or LTspice, if you prefer a GUI) and simulate the RC example in the repository's setup/ folder. You should get a rising exponential.
• Install Logisim Evolution and open the sample circuit in setup/.
• Create a GitHub account if you do not have one, install Git, and configure your name and email locally.
• Clone the course repository and push one commit to your own project repository containing a README.md with your name and your toolchain version output.
• Re-read these notes, sections 4 and 5 especially. Notes 02 picks up where they leave off, with the model of a stored bit that seeds Project 1 — whose specification is released next week.

10Exercises

Not graded. Bring your answers, or your stuck points, to Session 2 — we will work through them at the board.

1. A logic family running at V_DD = 1.2 V specifies V_OL = 0.10 V, V_IL = 0.42 V, V_IH = 0.78 V, V_OH = 1.10 V. Find both noise margins. Now suppose supply droop of 8% affects the driving gate's V_OH proportionally but not the receiver's thresholds. What is the high-side margin then?
2. A resistive voltage divider produces 0.5 V_DD from V_DD, and someone proposes labeling its input and output HIGH/LOW and calling it a buffer. Walk it through the five criteria of section 4 and identify every one it fails. Which single failure is fatal on its own?
3. A chain of 100 analog stages each adds an independent random error drawn uniformly from ±1% of full swing. Estimate the typical error at the output. Now pass the same signal through 100 digital stages with a 30% noise margin: what is the probability that even one stage flips the bit? What do the two answers, taken together, say about what "digital is more reliable" actually means — reliable against what?
4. Estimate, to within an order of magnitude, the largest chip across which a signal can travel in a single cycle at 4 GHz, assuming ideal transmission-line propagation in SiO₂. Compare with the physical size of a real processor die. What does the comparison imply about global signals?

§Symbols and constants