Switches, Inverters, and Static CMOS Gates

1Switches that compute

Start with the plainest thing in your house: a light switch. It has two states. Open means no path, so no current flows. Closed means a path, so current flows. That is already one bit.

Now take two switches and one lamp. There are only two ways to wire them.

• Series means one after the other, like two doors in a row. The lamp lights only if switch A and switch B are both closed.
• Parallel means side by side, like two doors into the same room. The lamp lights if switch A or switch B is closed (or both).

So the way you wire switches is the logic. Series gives AND. Parallel gives OR. Keep this one idea in your pocket. It will build every gate in these notes.

"1" means closed (a lever flipped on). "0" means open. Copper wire carries power; gray wire does not.

The redstone dictionary

Most of you have built logic in Minecraft redstone, so let's make it our running example. Here is how the words line up. We will add rows as we go.

Why do we care about switches at all? Notes 01 said a digital system needs parts that decide: they look at a messy voltage, call it 0 or 1, and pass on a clean one. A switch that is either fully open or fully closed is a decision-maker by nature. And in a chip, the switch is the transistor you met in Notes 05. Its gate is the handle. A voltage on the gate opens or closes the path between its other two ends. So one wire's voltage can flip a switch that controls another wire. That is the whole trick of computing with electricity: wires flipping switches that drive other wires.

2Two kinds of switch: NMOS and PMOS

CMOS uses two kinds of transistor switch. They are mirror images of each other. You only need one fact about each.

The little circle on the PMOS is a "not" sign. It reminds you that PMOS is on when its gate is not high. Two names you will see all the time: V_DD is the power supply, the "1" wire. In these notes it is 1.0 V. GND (ground) is the "0" wire, at 0 V.

Why not just use one kind?

Each kind is good in one direction and bad in the other. Here is the simple picture. An NMOS switch stays wide open only while its gate is clearly higher than the wire it is driving, by more than the threshold voltage (Notes 05; think of it as about 0.3 V here).

• NMOS pulling down to 0: the output falls toward 0 V. The gate sits at 1.0 V, way above. The switch stays wide open the whole way. The output reaches a clean 0. We call this a strong 0.
• NMOS pulling up to 1: the output climbs toward 1.0 V. But the gap between gate (1.0 V) and output keeps shrinking. At about 0.7 V the gap equals the threshold, and the switch closes itself. The output gets stuck short of the top. We call this a weak 1.

PMOS is the exact mirror. It gives a strong 1 and a weak 0. So the deal writes itself: use PMOS to connect the output to 1, and NMOS to connect it to 0. Each switch only does the job it is good at. That pairing is the "C" in CMOS: complementary, meaning two parts that complete each other.

3The CMOS inverter

Put one PMOS on top, between V_DD and the output. Put one NMOS on the bottom, between the output and ground. Tie both gates to the same input, A. That's it. Two transistors. This is the CMOS inverter, the NOT gate.

Think of a seesaw. When one end is up, the other is down. Never both.

• A = 0: PMOS is on (its gate is low). NMOS is off. The output is connected to V_DD. Output = 1.
• A = 1: PMOS is off. NMOS is on (its gate is high). The output is connected to ground. Output = 0.

The redstone torch is an inverter

You already know this gate. In Minecraft redstone, a torch stuck on a block is on when the block is unpowered, and off when the block is powered. Power in, no power out. No power in, power out. That is NOT. The CMOS inverter does the same job with a switch pair: whenever one switch closes, the other opens. One torch = one PMOS + one NMOS.

Figure 3.1. Top: redstone lever → dust → block with torch → lamp. Bottom: the CMOS inverter at the same input. A closed (ON) switch is drawn as a solid bar; an open (off) one has a gap.

Two things the inverter gets right

1. The output is always firmly held. At any steady input, exactly one switch is on. So the output is always connected to V_DD or to ground. Never both. Never neither. This is what static means in "static CMOS". Section 8 comes back to it.

2. It uses almost no power while it sits still. Picture a water pipe from a tank (V_DD) down to a drain (ground), with two valves in it. One valve is always shut. So no water runs from the tank to the drain. Water only moves when the output changes: the output wire has to be filled up (to make a 1) or emptied (to make a 0). That fill-and-empty is exactly the ½CV² per flip you priced in Notes 03. There is also a tiny leak through "off" switches, which we save for week 11.

4The inverter's curve: a cliff

So far the input was a clean 0 or a clean 1. But a real wire can be at any voltage: 0.2 V, 0.48 V, anything. What does the inverter do then? Plot the output voltage against the input voltage and you get its voltage transfer characteristic, or VTC. That is a fancy name for "the input-output curve".

The curve is shaped like a cliff. On the left it is flat at 1.0 V: a low-ish input still gives a solid 1. On the right it is flat at 0 V. In the middle it drops very steeply. Where exactly it drops is called the switching point, V_M: the input where output equals input. For a balanced inverter it sits near the middle, 0.5 V.

A simple textbook transistor model with V_DD = 1.0 V and thresholds of 0.3 V. "Pull-up strength" makes the PMOS stronger or weaker than the NMOS (1× = balanced). The shaded band is the forbidden zone, where the curve is steeper than 45°.

Why the cliff matters: noise margins, again

Remember Notes 01's static discipline. A gate must accept anything below V_IL as a 0 and anything above V_IH as a 1. Between them is the forbidden zone. The inverter's curve tells us where those lines really are. We put them where the curve gets steeper than 45°. Outside them, wiggles on the input barely move the output. Inside, small wiggles become big swings.

CMOS outputs go all the way to the rails, 0 V and 1.0 V. So the noise margins are simply: low margin = V_IL − 0, and high margin = 1.0 − V_IH. For the balanced inverter on the bench, both are about 0.44 V. That is almost half the supply on each side. Generous.

And the steep middle does Notes 01's restoration for free. A slightly-bad 0 at 0.15 V comes out as a near-perfect 1. Then the next inverter turns that into a perfect 0. Noise is cleaned up at every stage, just like Bench 5.1 of Notes 01 showed. Now you can see the part that actually does the cleaning.

Two more things to try on the bench. First, watch "current straight through". It is zero at both ends and peaks in the middle. That is the brief moment, mid-flip, when both switches are partly open and some water runs straight from tank to drain. Second, slide the pull-up strength. A stronger PMOS drags the switching point to the right, and one noise margin shrinks while the other grows. Balancing the two is a real design choice. You will make it in Project 2.

5Building gates: NAND and NOR

Every static CMOS gate has the same shape as the inverter. It just has more switches in each half.

• The pull-up network is made of PMOS switches. It sits between V_DD and the output. When it is on, it pulls the output up to 1.
• The pull-down network is made of NMOS switches. It sits between the output and ground. When it is on, it pulls the output down to 0.

The one rule: for every input, exactly one of the two networks is on. Section 1 gave us the tools: series means "all must be on", parallel means "any one is enough".

NAND: "output is 0 only if A and B are both 1"

Pull-down: two NMOS in series. Both must be on to reach ground, so the output goes to 0 only when A = 1 and B = 1. Pull-up: two PMOS in parallel. Either one can pull the output up, so the output is 1 whenever A = 0 or B = 0. Together: NOT (A AND B). Four transistors.

NOR: "output is 0 if A or B is 1"

Flip it around. Pull-down: two NMOS in parallel, so either input being 1 pulls the output to 0. Pull-up: two PMOS in series, so the output is 1 only when A = 0 and B = 0. Together: NOT (A OR B). Also four transistors.

See the pattern? Series in one network means parallel in the other. The two networks are mirror images, called duals. This is what guarantees the one rule. Whenever the bottom has a path, the top is broken somewhere, and the other way around. The seesaw from section 3, with more switches on each end.

The same gates in Minecraft redstone

Redstone builders know these as classic builds. Line them up with the transistors and they match surprisingly well.

• Redstone NOR: two lever lines merge into one (an OR), and the merged line powers a block with a torch. The torch inverts it. In CMOS, the "merge" is the two NMOS in parallel: either input pulls the output down.
• Redstone NAND: each lever powers its own block with a torch, and the two torch outputs merge into one line. Each torch is "on when its lever is off". In CMOS, that is exactly a PMOS (on when its input is 0), and the two PMOS sit in parallel: the merge.
• Redstone AND (the "torch AND"): the NAND build plus one more torch at the end. Section 6 shows CMOS does the very same thing.

Flip the bench below to "Redstone" view to see each build next to its transistor version. Same inputs, same lamp.

Click a truth-table row to jump to those inputs. AOI21 is introduced in section 6. In redstone view the diagrams are simplified layouts on a grid, not exact block-by-block builds; dust that is part of one connected line is powered together, as in the game.

6Inverted by nature, and the recipe for any gate

Notice that every gate so far had a "NOT" in front: NOT, NAND, NOR. That is not an accident. Think about what happens when an input goes from 0 to 1. It can only turn NMOS switches on (pulling down) and PMOS switches off (letting go of the top). Either way, the output can only be pushed down. Raising an input can never raise the output. So a single static CMOS gate is always inverting.

Want a plain AND? Build a NAND, then add an inverter: 4 + 2 = 6 transistors. Want OR? NOR plus an inverter. That is why chip designers think in NAND and NOR first. They are the cheapest gates there are.

Redstone players already know this move. The torch AND is literally "NAND, then one more torch". Dust alone can only merge lines (OR). To get AND, you have to invert.

The merged line after the first two torches is a NAND (lit unless both levers are on). The last torch inverts it into AND. In CMOS: a NAND gate followed by an inverter.

The recipe for any gate

NAND and NOR are not special. Any "NOT of some AND/OR mix" can be built in one stage. Here is the recipe:

1. Write the function as Y = NOT( something ).
2. Build the pull-down from the "something": every AND becomes NMOS in series, every OR becomes NMOS in parallel.
3. Build the pull-up as the dual: swap every series for parallel and every parallel for series, using PMOS.

Gates built this way are called complex gates. A famous one is the AND-OR-INVERT gate, or AOI.

One limit: complex gates cannot grow forever. A chain of many switches in series is slow, and we will see exactly why in week 8. And how to connect many gates into bigger circuits, like adders, is next week's topic.

7Build a gate: what goes wrong

What if you break the dual rule? Two things can go wrong, and both are bad.

• Both networks on: V_DD is wired straight to ground through the gate. This is a short. The two networks fight, like two people pulling a rope in opposite directions. The output ends up somewhere in the middle, and current pours through, wasting power and heating the chip.
• Both networks off: the output is connected to nothing. It is floating, like a door that is neither latched open nor latched shut, just swinging. It keeps whatever charge it had, and any nearby noise can push it around.

Try it. Pick the two networks below and the bench checks every input for you.

"Up" and "Down" columns show whether each network connects the output to its rail. A valid static gate has exactly one "on" in every row. Hint: start by making the two networks duals.

8What "static" buys us, and a family that isn't

Let's say clearly what the word means. In a static CMOS gate, for every steady input, the output is connected to exactly one rail, through switches that are fully on. That buys three things:

• Full swing. Outputs are exactly 0 V or 1.0 V. Biggest possible noise margins.
• No fighting. The networks never pull against each other at rest, so no current flows at rest (only the tiny leak).
• Holds forever. The output is actively held, not just remembered. Leave the inputs alone for an hour and the output is still solid.

The family name for all these gates (inverter, NAND, NOR, AOI, and friends) is static CMOS. It is what nearly every chip uses for nearly all of its logic.

A contrast: pseudo-NMOS, the gate that always fights

Not every logic family works this way. Here is an older trick. Replace the whole pull-up network with one PMOS whose gate is tied to ground. Its gate is always low, so it is always on. It acts like a weak spring always pulling the output up. The NMOS network then has to win a tug-of-war against it to make a 0. This is called pseudo-NMOS.

Figure 8.1. Pseudo-NMOS inverter. The top PMOS is always on. When A = 1, both switches are on at once, and current flows from V_DD to ground for as long as A stays 1.

It does work, sort of. The NMOS is made stronger than the PMOS, so the output gets near 0. But it never quite reaches 0, so the low noise margin shrinks. And whenever the output is 0, current flows nonstop, burning power even when nothing is changing. Because the output depends on how strong one transistor is compared with the other, this kind of family is called ratioed logic. Static CMOS is ratioless: the output is right no matter how strong each switch is. The strength only changes the speed.

Fewer transistors is tempting. But a billion gates each leaking current all the time is a melted chip. That is why static CMOS won.

9Project 2 opens this week

The Project 2 specification, CMOS Logic: Speed and Energy, is released this week. You will design a small CMOS logic block, simulate it, and measure its delay, its power (both while switching and while sitting still), and its noise margins, across several supply voltages and loads. Then you write up the trade-off between energy and speed.

This week hands you about half the vocabulary:

• Designing the block: sections 5–7. Pull-up, pull-down, duals.
• Noise margins: section 4. In simulation you will sweep the input of a gate and read V_IL and V_IH off its curve, just like Bench 4.1.
• Static power: sections 3 and 8. In static CMOS it should be tiny; if yours is not, something is fighting.
• Dynamic power: Notes 03's ½CV², once per flip.
• Delay: not yet. That is week 8, just in time for the due date.

10Self-check

Seven quick questions. Click an answer to see why. Nothing is recorded.

→Before next week

Session 11 is Monday, October 12. Before then:

• Review Notes 06. Sections 3, 5, and 6 most of all.
• Play with Bench 5.1 until you can call the output, and name which transistors are on, before you click. Do all four gates.
• Read the Project 2 specification when it is released. Write down one question about it and bring it Monday.
• On paper, use the recipe from section 6 to draw a static CMOS gate for Y = NOT( (A + B) · C ). Count the transistors. (Check: it is the dual of AOI21, called OAI21.)
• Optional, and a head start on Project 2: if you already have an inverter running in ngspice or LTspice, sweep its input from 0 to V_DD and plot the output. Compare it with Bench 4.1.

§Words to know